1. Field of the Invention
The present invention relates to memory access methods and devices for use with random access memories and, in particular but not exclusively, with synchronous dynamic random access memories (SDRAMs).
2. Description of the Related Art
SDRAM devices are designed so as to be simpler to use than standard dynamic random access memories (DRAMs) which suffer from many control signal timing constraints. The data bandwidth of such an SDRAM device may be as much as 5 times that of a standard DRAM, making the SDRAM device ideally suited for use in, for example, laser printers, high resolution graphic adapters, accelerators, and other applications where an extremely large memory and bandwidth are required.
A typical organisation of an SDRAM device is shown in FIG. 1 of the accompanying drawings. Such a device is described, for example, in detail in xe2x80x9cProduct Profile Sheet: MB811171622A CMOS 2xc3x97512Kxc3x9716 Synchronous DRAMxe2x80x9d, Fujitsu Limited, July 1996.
At the core of the SDRAM device 1 are two banks 2 and 3, each of which is constituted by a matrix of memory cells. In each bank, the matrix is organised to provide storage for 512K words of 16 bits (K=1024). A total of 20 address input signals are required to identify a particular word in one of the banks 2 or 3. To reduce the pin count of the device, an 11-bit row address A0 to A10 is supplied first to an address buffer/register 4 of the device, whereafter an 8-bit column address A0 to A7 is applied to the address buffer/register 4. A further address bit A11 is used as a bank select signal for selecting either the first bank 2 or the second bank 3 of the device.
The SDRAM device 1 further comprises a clock buffer 5, command decoder 6, input/output data buffer/register 7, control signal latches 8 and 9 corresponding respectively to the two banks 2 and 3, a mode register 10, and column address counters 11 and 12 corresponding respectively to the banks 2 and 3. The constitution and operation of the elements of the SDRAM device 1 shown in FIG. 1 are well-known in the art and so will not be described further herein.
There are three major differences between the SDRAM device 1 and a conventional DRAM. The first, and most important, difference is that the SDRAM operates synchronously using a clock input for synchronisation purposes, whereas the conventional DRAM is essentially an asynchronous memory device even though it makes use of timing signals RAS and CAS. In the conventional DRAM, each operation is determined by the phase differences between these two timing signals, whereas in the SDRAM device 1 of FIG. 1, each operation is determined by commands and all operations are referenced to a positive clock edge.
The SDRAM device 1 of FIG. 1 also differs from the conventional DRAM in that it is capable of operating in a burst mode which is a very high speed access mode (read or write) utilising the internal column address counters 11 and 12. Once a column address for the first access is set, the following addresses are automatically generated by one of the internal column address counters 11 or 12.
Further, the SDRAM device 1 of FIG. 1 differs from the conventional DRAM in having the mode register 10 which serves to configure the SDRAM operations and functions so as to achieve desired system conditions.
Each bank 2 or 3 in FIG. 1 contains multiple pages, for example there may be 2K pages, each containing 256 words. To access (read or write) an item of information within a page, the bank containing the page must-be in a defined state, i.e. the bank must have been precharged, and the page must have been activated. These precharge and activation operations require clock cycles. Accordingly, a precharge is best carried out when accessing of one page is finished with, so that the next page is then ready for immediate activation when required.
As mentioned above, SDRAM devices are synchronous devices, and actions are carried out on the positive clock edge. An SDRAM device can be programmed to process commands after n clock cycles (n=1, 2 or 3), and n=3  usually enables the highest throughput.
Information can be accessed in bursts, but (unfortunately for ease of use) the leading and trailing parts (protocols) of the access sequence differ between reads and writes. The burst length can be programmed, but is usually set to either 4 or 8 words, particularly when the accesses are relatively short and random. Bursts can be terminated automatically by precharge commands, or these can be issued explicitly. Automatically terminated read bursts give performance advantages, but automatically terminated write bursts do not (in this case the automatic precharge command simply eliminates the need to issue an explicit precharge command).
Bursts that are not automatically terminated by precharge can be interrupted and terminated by other bursts, but it is best to terminate reads with reads and writes with writes, and to ensure that the final burst access is of the automatically precharged type.
SDRAM devices naturally achieve high throughputs of information if the burst lengths are greater than eight words (sufficient to hide the leading and trailing read and write access protocols), and banks can be continually interleaved. However, these criteria are not easy to achieve in some of the applications in which SDRAM devices are normally considered for use. For example, in asynchronous transfer mode (ATM) communication systems, SDRAM devices are considered attractive for storing information items (e.g. transient control parameters) relating to ATM cells. If the ATM cells are to be processed at rates of 622 MHz or higher, the cell lifetimes are relatively short, for example 680 ns. The processing of cells is normally pipelined, so that, within a single ATM cell lifetime (680 ns), it may be necessary to write one or more information items and to read one or more information items. To secure the expected benefits (e.g. performance and memory depth) of SDRAM devices in such demanding situations, it is therefore desirable to provide improved methods and devices for accessing information items stored in SDRAM devices.
The same requirements can arise in random access memory systems not employing SDRAM devices. For example, so-called Rambus devices are commercially available (example devices are the NEC uPD488130L and the Toshiba TC59R0808HK) which, in common with SDRAM devices, have two (or more) banks which share a common data bus. Rambus DRAMs (or RDRAMS) are developed and marketed by Rambus Inc., a high-speed interface technology company, and can transfer data at 600 megabytes per second or more over a so-called Rambus Channel, a narrow byte-wide data bus. Rambus DRAMs can provide 8 times the bandwidth per pin of alternative high-speed DRAM components. Rambus memories are accessed using protocols that require a relatively high number of clock cycles to initiate the access (even more than SDRAM devices). In these Rambus devices, additional clock cycles also elapse before the data starts to be transferred. To try to maintain high effective throughput rates, the size of the data transfer (burst) is usually about 32 or more bytes. Furthermore, SyncLink devices (SyncLink is a consortium of DRAM manufacturers whose goal is to create an industry standard for a new DRAM architecture which allows data transfer rates of 500 Mbytes up to 3.2 Gbytes per second) are random access memory devices with a single input/output of high bandwidth which also use protocols broadly similar to Rambus protocols.
Even in the case of random access memory systems which do not employ plural-bank individual devices (such as SDRAM devices or Rambus devices) there may arise a demand to read one or more information items from the memory and to write one or more information items to the memory in the same time slot, the duration of this time slot being less than the total time required to access the items sequentially. For example, such a demand may arise in a disk storage system or in a static random access memory (SRAM) system.
According to a first aspect of the present invention there is provided a memory access method, for use with a random access memory having first and second storage portions, which method comprises: allocating each information item respective first and second storage locations in the said memory, which first and second storage locations are in the said first and second storage portions respectively; and in the same time slot, writing a first such information item in the memory and reading a second such information item from the memory by carrying out the steps of: a) determining which of the first and second storage locations allocated to the said second information item currently holds that item; b) writing the said first information item in the said first storage location allocated thereto if the determined storage location is such a second storage location and writing the first information item in the said second storage location allocated thereto if the determined storage location is such a first storage location; and c) reading the said second information item from the said determined storage location.
The random access memory may comprise just one random access memory device that has, internally, two different storage portions that are accessed externally via a common or shared data bus. For example, an SDRAM device has two (or more) different banks that are accessed externally via a common data bus. Similarly, a Rambus device or SyncLink device also has plural banks that are accessed via a common data bus. The two storage portions could even be two different data storage surfaces of a disk drive unit that are accessed, externally of the unit, via a common data bus. In these cases, the writing step (b) and reading step (c) must be carried out sequentially because the common data bus constitutes a xe2x80x9cdata bottleneckxe2x80x9d. However, because each information item is allocated two different storage locations in different respective storage portions, it is always possible to perform the write operation in a different storage portion from the read operation (bank interleaving), so that the writing step (b) can partially overlap with the reading step (c), thereby xe2x80x9chidingxe2x80x9d some of the leading or trailing protocols of the two access operations. Thus, the minimum duration of the time slot can be less than the sum of the duration of an individual read operation and the duration of an individual write operation, where the read and write operations are from/to the same bank.
In one preferred embodiment the writing of the first information item is performed before the reading of the said second information item. This provides greater throughput of data when the first and second banks form part of the same synchronous dynamic random access memory device.
Alternatively, the random access memory may comprise plural individual random access memory devices such as plural semiconductor RAM devices (e.g. SDRAM devices, static RAM devices, dynamic RAM devices, Rambus devices, SyncLink devices) or any arrangement providing two randomly-accessible storage portions, e.g. two disk drive units providing respective data storage surfaces (magnetic or optical, and hard or floppy), or even two data storage surfaces within the same disk drive unit provided that the two data storage surfaces are accessible independently via different data buses. In these cases, because each information item is allocated two different storage locations in different respective storage portions (e.g. in different semiconductor RAM devices or on different data storage surfaces), it is always possible to perform the write operation on a storage portion that is not being read in the read operation. This enables the writing step (b) to be performed in parallel with the reading step (c) so that the longer of the two steps can completely overlap the shorter of the two steps. Thus, the minimum duration of the time slot is simply equal to the duration of the longer step.
In all cases, the first and second information items may be one and the same information item.
In one embodiment, each information item has a corresponding pointer indicating in which of the first and second storage locations allocated thereto the item concerned is currently held. In step (a) the determination of the storage location currently holding the said second information item is made using the pointer corresponding to that item; and the pointer corresponding to the said first information item is updated to indicate in which of the first and second storage locations allocated thereto the item concerned is written in step (b).
According to a second aspect of the present invention there is provided a memory access method, for use with a random access memory having first and second storage portions that are accessed via a common data bus, which method comprises: allocating each information item a first storage location for storing a first part of the item and a second storage location for storing a second part of the item, the first and second storage locations being in the said first and second storage portions respectively; in the same time slot, writing a first such information item in the memory and reading a second such information item from the memory by carrying out in a predetermined sequence the steps of a) writing the said first part of the said first information item in the said first storage location allocated to that item; b) writing the said second part of the said first information item in the said second storage location allocated to that item; c) reading the said first part of the said second information item from the said first storage location allocated to that item; and d) reading the said second part of the said second information item from the said second storage location allocated to that item.
The first and second storage portions may be provided respectively by two different banks of the same synchronous dynamic random access memory device or of the same Rambus or SyncLink device. Alternatively, the first and second storage portions may be provided by two different data storage surfaces of the same disk drive unit.
This access method splits an individual information item across two different storage portions, which can then always be accessed as an interleaved pair while utilising all of the memory for storage. As bursts approach eight or more words in length in an SDRAM, it becomes easier to hide bank swapping overheads. This method has a slightly-reduced throughput, as compared to the basic dual-bank access method embodying the aforesaid first aspect of the present invention, but has the advantage of providing 100% memory utilisation.
To enhance throughput the said predetermined sequence in which the said steps (a) to (d) are performed preferably includes at least one pair (more preferably still, two pairs) of successive steps in which the first step of the pair is a write to one of the two storage portions (banks) and the second step of the pair is a read of the other of the two storage portions (banks). For example, in one preferred embodiment the said sequence is step (a) followed by step (d) followed by step (b) followed by step (c).
The first and second information items may be one and the same information item.
The said first and second parts of each information item may be of the same length, or alternatively the length of the said first part of each information item may be different from the length of the said second part of each information item. In the latter case it is preferable, from the point of view of throughput, that the last step of the sequence in which the said steps (a) to (d) are performed is the step of reading the longer of the two parts of the said second information item.
It is also useful, when the lengths of the first and second parts of each information item are different, to make the length of the shorter of the two parts of each said information item less than or equal to the number of words that can be accessed in a single burst. Because the shorter part can be accessed in a single burst, the overall number of commands and addresses required to complete steps (a) to (d) is reduced. In this way, design complexity can be reduced or additional sequence flexibility is facilitated.
The storage location allocated for storing the shorter of the two parts of each information item may be longer than that shorter part, so that spare words in that storage location can be used for storing information other than the information-item part to which that storage location is allocated. Preferably, the number of spare words is equal to the number of words that can be accessed in a single burst. This makes access to the spare words efficient.
According to a third aspect of the present invention there is provided a memory access method, for use with a random access memory having respective first and second storage portions that are accessed via a first common data bus and also having respective third and fourth banks that are accessed via a second common data bus, which method comprises: allocating each information item respective first, second, third and fourth storage locations in the first, second, third and fourth storage portions respectively; and in the same time slot, writing first and second such information items in the memory and reading third and fourth such information items from the memory by carrying out the steps of: a) determining which of the storage locations allocated to the third information item currently holds that item and determining which of the storage locations allocated to the fourth information item currently holds that item, and identifying the storage portion(s) in which the two determined storage locations are included; b) writing the first and second information items to respective storage locations in two different storage portions other than the identified storage portion(s); and c) reading the said third and fourth information items from their respective determined storage locations.
By allocating each information item four different storage locations in different respective storage portions, the two write operations can always be performed on storage portions that are not being read. Usually (i.e. except when the third and fourth information items are held in the same storage portion) it is possible, for each pair of storage portions that share a common data bus for access, to perform a read from one storage portion of the pair and a write to the other storage portion of the pair, the read and the write being capable of partially overlapping because they are from/to different storage portions of the same access pair. Thus, the minimum duration of the time slot can be less than the sum of the respective durations of non-interleaved read and write operations. Also, even when the third and fourth information items are held in the same storage portion, the two writes are both carried out in the two different storage portions of a single access pair, making it possible to benefit from write interleaving.
The said first and second storage portions may be provided respectively by two different banks of a first synchronous dynamic random access memory device, and the said third and fourth storage portions may be provided respectively by two different banks of a second synchronous dynamic random access memory device. In this case, when it is identified in step (a) that the determined storage locations for the third and fourth information items are included in different respective banks and that one of those banks forms part of the first synchronous dynamic random access memory device whilst the other of those banks forms part of the said second synchronous dynamic random access memory device, in each such device the writing of step (b), to the bank other than the identified bank of the device concerned, is performed before the reading of step (c) from that identified bank. This has the effect of increasing throughput.
Alternatively, the first and second storage portions may be provided by two different banks of a first Rambus or SyncLink device and the third and fourth storage portions may be provided by two different banks of a second Rambus or SyncLink device. As a further possibility, the first and second storage portions may be provided by two different data storage surfaces of a first disk drive unit and the third and fourth storage portions may be provided by two different data storage surfaces of a second disk drive unit.
One of the items being read may be the same as one of the items being written, or both items being read may be the same as the items being written.
In one preferred embodiment, each said information item has a corresponding pointer indicating in which of the said first, second, third and fourth storage locations allocated thereto the item concerned is currently held. In step (a), for each of the third and fourth information items, the determination of the storage location currently holding the item concerned is made using the pointer corresponding to that item. Furthermore, for each of the first and second information items, the pointer corresponding to the item concerned is updated to indicate in which of the first, second, third and fourth storage locations allocated thereto the item concerned is written in step (b).
According to a fourth aspect of the present invention there is provided a a memory access method, for use with a dynamic random access memory having respective first and second storage portions that are accessed via a first common data bus and also having third and fourth storage portions that are accessed via a second common data bus, which method comprises: allocating each information item respective first and second pairs of storage locations, each pair being made up of a first storage location for storing a first part of the item concerned and a second storage location for storing a second part of the item concerned, the said first and second storage locations of the first storage-location pair being in the first and second storage portions respectively and the said first and second storage locations of the second storage-location pair being in the third and fourth storage portions respectively; and in the same time slot, writing first and second such information items in the memory and reading third and fourth such information items from the memory by carrying out the steps of: a) determining, for each of the third and fourth information items, which of the first and second pairs of storage locations allocated to the item currently holds the item; b) writing the first and second parts of the first information item in the first and second storage locations respectively of the storage-location pair other than the determined storage-location pair for the third information item; c) writing the first and second parts of the second information item in the first and second storage locations respectively of the storage-location pair other than the determined storage-location pair for the fourth information item; d) reading the first and second parts of the third information item from the first and second storage locations respectively of the determined storage-location pair for that item; and e) reading the first and second parts of the fourth information item from the first and second storage location respectively of the determined storage-location pair for that item.
This access method is effectively a combination of the access methods embodying the first and second aspects of the present invention, i.e. a combination of the dual banks and split banks access methods. As compared to the access method embodying the third aspect of the invention, which only has 25% memory utilisation, the access method embodying the fourth aspect of the invention achieves 50% memory utilisation, although at the expense of slightly reduced throughput.
One of the items being read may be the same as one of the items being written, or both items being read may be the same as the items being written.
The said first and second banks may both form part of a first synchronous dynamic random access memory device, and the said third and fourth banks may both form part of a second synchronous dynamic random access memory device. In this case, when it is determined that the third and fourth information items are currently held in different respective storage-location pairs (i.e. in different respective devices), it follows that in each of the said first and second devices one of the said writing steps (b) and (c) and one of the said reading steps (d) and (e) are to be carried out. To increase throughput it is preferable in this case that the writing step and reading step in each device are carried out in the following sequence: writing the first part of the information item to be written in the said writing step; reading the said second part of the information item to be read in the said reading step; writing the second part of the information item to be written in the said writing step; and reading the first part of the information item to be read in the said reading step.
Similarly, when it is determined that the third and fourth information items are both currently held in the same storage-location pair (i.e. in the same device), it follows that the two reading steps (d) and (e) are both to be carried out in the same one of the two devices. Again, to increase throughput, the two banks of that device are preferably read alternately in the course of carrying out the reading steps (d) and (e). Similarly, the two writing steps (b) and (c) are both to be carried out in the other of the two devices. To increase throughput, the two banks of that device are preferably written alternately in the course of carrying out the writing steps (b) and (c).
Alternatively, the first and second storage portions may be provided by two different banks of a first Rambus or SyncLink device and the third and fourth storage portions may be provided by two different banks of a second Rambus or SyncLink device. As a further possibility, the first and second storage portions may be provided by two different data storage surfaces of a first disk drive unit and the third and fourth storage portions may be provided by two different data storage surfaces of a second disk drive unit.
In one preferred embodiment, each information item has a corresponding pointer indicating in which of the first and second storage-location pairs allocated thereto the item concerned is currently held. In step (a), for each of the third and fourth information items, the determination of the storage-location pair currently holding the item concerned is made using the pointer corresponding to that item. Also, for each of the said first and second information items, the pointer corresponding to the item concerned is updated to indicate in which of the first and second storage-location pairs allocated thereto the item concerned is written in step (b) or (c).
According to a fifth aspect of the present invention there is provided memory access circuitry, for use with a random access memory having first and second storage portions, which circuitry comprises: allocation means for allocating each information item respective first and second storage locations in the said memory, which first and second storage locations are in the said first and second storage portions respectively; determining means, operable when in the same time slot a first such information item is to be written in the memory and a second such information item is to be read from the memory, to determine which of the first and second storage locations allocated to the said second information item currently holds that item; writing means for writing the said first information item in the said first storage location allocated thereto if the storage location determined by the determining means is such a second storage location and for writing the first information item in the said second storage location allocated thereto if the storage location determined by the determining means is such a first storage location; and reading means for reading the said second information item from the said determined storage location.
According to a sixth aspect of the present invention there is provided memory access circuitry, for use with a random access memory having first and second storage portions that are accessed via a common data bus, which circuitry comprises: allocation means for allocating each information item a first storage location for storing a first part of the item and a second storage location for storing a second part of the item, the first and second storage locations being in the said first and second storage portions respectively; first writing means for writing the said first part of the said first information item in the said first storage location allocated to that item; second writing means for writing the said second part of the said first information item in the said second storage location allocated to that item; first reading means for reading the said first part of the said second information item from the said first storage location allocated to that item; second reading means for reading the said second part of the said second information item from the said second storage location allocated to that item; and access control means operable, when in the same time slot a first such information item is to be written in the memory and a second such information item is to be read from the memory, to activate each of the said first and second writing means and each of the said first and second reading means once in a predetermined sequence.
According to a seventh aspect of the present invention there is provided memory access circuitry, for use with a random access memory having respective first and second storage portions that are accessed via a first common data bus and also having respective third and fourth storage portions that are accessed via a second common data bus, which circuitry comprises: allocation means for allocating each information item respective first, second, third and fourth storage locations in the first, second, third and fourth storage portions respectively; and determining means, operable when in the same time slot first and second such information items are to be written in the memory and third and fourth such information items are to be read from the memory, to determine which of the storage locations allocated to the third information item currently holds that item and to determine which of the storage locations allocated to the fourth information item currently holds that item, and to identify the storage portion in which the two determined storage locations are included; writing means for writing the first and second information items to respective storage locations in two different storage portions other than the storage portion(s) identified by the determining means; and reading means for reading the said third and fourth information items from their respective storage locations determined by the determining means.
According to an eighth aspect of the present invention there is provided memory access circuitry, for use with a random access memory having respective first and second storage portions that are accessed via a first common data bus and also having respective third and fourth storage portions that are accessed via a second common data bus, which circuitry comprises: allocation means for allocating each information item respective first and second pairs of storage locations, each pair being made up of a first storage location for storing a first part of the item concerned and a second storage location for storing a second part of the item concerned, the said first and second storage locations of the first storage-location pair being in the first and second storage portions respectively and the said first and second storage locations of the second storage-location pair being in the third and storage portions respectively; determining means operable, when in the same time slot first and second such information items are to be written in the memory and third and fourth such information items are to be read from the memory, to determine, for each of the third and fourth information items, which of the first and second pairs of storage locations allocated to the item currently holds the item; first writing means for writing the first and second parts of the first information items in the first and second storage locations respectively of the storage-location pair other than the storage-location pair determined for the third information item by the determining means; second writing means for writing the first and second parts of the second information item in the first and second storage locations respectively of the storage-location pair other than the storage-location pair determined for the fourth information item by the determining means; first reading means for reading the first and second parts of the third information item from the first and second storage locations respectively of the determined storage-location pair for that item; and second reading means for reading the first and second parts of the fourth information item from the first and second storage location respectively of the determined storage-location pair for that item.
According to a ninth aspect of the present invention there is provided synchronous dynamic random access memory apparatus including: respective first, second and third synchronous dynamic random access memory devices, each device having two banks; and access control means connected to the said first, second and third devices and operable to cause mutually-corresponding banks of the first and second devices to be accessed in parallel with one another, whilst permitting the banks of the said third device to be accessed individually.
Such apparatus can enable information items of different lengths to be accessed conveniently and at high speed.
To enhance the flexibility of the apparatus, a burst length of the said first and second devices may be different from a burst length of the said third device. Alternatively, or in addition, the banks of one (or each) of the devices may be of a different width from those of another (or each other) of the devices.
According to a tenth aspect of the present invention there is provided synchronous dynamic random access memory apparatus including respective first and second synchronous dynamic random access memory devices, each device having two banks, and the banks of the first device being of a different width from the banks of the second device.
Such apparatus can also enable information items of different lengths to be accessed conveniently and at high speed.
According to an eleventh aspect of the present invention there is provided synchronous dynamic random access memory apparatus including: a plurality of (e.g. more than 3 or more than 4) synchronous dynamic random access memory devices operable synchronously in accordance with clock cycles; and memory access means connected to each said device of the said plurality by way of a common control bus through which the memory access means supply commands and addresses to the devices in parallel so as to cause the devices to perform predetermined access operations in parallel, the said commands and addresses each occupying a period of more than one said clock cycle.
In such apparatus, although the lines of the common control bus are heavily loaded, by allowing each command and address to be supplied over more than one clock cycle (e.g. 2 clock cycles) the devices can still operate correctly. By using longer bursts it is possible to avoid command clashes. The control pin count is reduced.
Preferably, the devices are deactivated using their respective chip select signals (which signals can be changed at the clock-cycle repetition rate) when, during the command-supply period, the lines of the common control bus used to supply commands and addresses to the devices are not yet settled.